Product features:
1.Lattice original design scheme is stable and reliable.
2. adopt current limiting and electrostatic protection to ensure full confidence.
3. support target IO voltage 1.2V to 5V,
4. supports all LATTICE development environments (LSC ISPVM, LATTICE DEMIOND, LATTICE ISPEVER,
And LATTICE PROGRAMMER),
5. support Lattice full range of FPGA, such as SC (M) /XP/XP2/ECP2 (M) /ECP3/ECP5 (G) /MachXO/MachXO2/MachXO3/ICE40 series,
6. support Lattice full range of CPLD, such as 1000/2000/4000/ispMACH series,
7. support JTAG, internal FLASH, SPI FLASH and other programming mode,
8. no need to install the driver separately, directly supporting Diamond/ispLever6.x/7.x/classic/ispVM version driver.
9.USB power supply, without external power supply,
10. adopt Lattice official 2*5Pin spacing 2.54mm JTAG interface,
11. support operating system Win2000/XP, Win7/8/10, Linux, etc.
Pin link Description:\
1.SCLK/TCK: connect to the SCLK/TCK pin of the chip,
2.GND: the Downloader is connected to the common ground of the target board and its internal 2 or 4 pins. When it is used, it needs to connect one foot of the 2 and 4 to the target board.
3.MODE/TMS: connect to the MODE/TMS pin of the chip,
4.GND: the Downloader is connected to the common ground of the target board and its internal 2 or 4 pins. When it is used, it needs to connect one foot of the 2 and 4 to the target board.
5.SDI/TDI: connect to the SDI/TDI pin of the chip,
6.VCC: the target board used to detect whether the Downloader is connected to the target board is not used to power the target board. The official downloader does not have the power to supply the target board. This needs to be paid attention to.
7.SDO/TDO: connect to the SDO/TDO pin of the chip,
8.INTI: when some chips are downloaded and debugged, they need to connect INTI pins, not every chip needs to be connected.
9.TRST: when some chips are downloaded and debugged, they need to connect TRST pins, not every chip needs to be connected.
10.ispEN/Enable/PROG: when some chips are downloaded and debugged, they need to connect ispEN/Enable/PROG pins, not every chip needs to be connected.
Recommended pin connection diagram:
Specifications
Material
+
Origin
Mainland China